Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with

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A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression.Characteristics of the device have been investigated based on physical models for material properties and improved trap models.By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate (BG-FP) structure,it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate-drain capacitance(C_(gd)) under a large drain voltage.A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less C_(gd) than a conventional FP.For microwave applications,4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel.For high power applications,the proposed structure is able to endure higher operating voltage as well.The maximum saturation current density of 460 mA/mm is yielded.Also,the gate-lag ratio under a drain voltage of 20 V is close to 90%.In addition,5%and 17.8%improvements in f_T and f_(max) are obtained compared with a BG-FP MESFET in AC simulation,respectively.Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design. A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression. Characteristics of the device have been investigated based on physical models for material properties and improved trap models. Comparison of the performance of the well-utilized buried-gate incorporated with a field-plate (BG-FP) structure, it shows the proposed structure improves device properties in a comprehensive aspect. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate- C_ (gd)) under a large drain voltage. A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less C_ (gd) than a conventional FP.For microwave applications , 4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel. For high power applications, the proposed struc ture is able to endure higher operating voltage as well. maximum saturation current density 460 mA / mm is yielded.Also, the gate-lag ratio under a drain voltage of 20 V is close to 90% .In addition, 5% and 17.8% improvements in f_T and f_ (max) are obtained compared to a BG-FP MESFET in AC simulation, respectively. Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.
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