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This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol.In order to reduce the die area,an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted.A low power clock generator is designed to guarantee the accuracy of the clock under±4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor,the total power consumption of the tag is about 14μW with a sensitivity of-9.5 dBm.The detection distance can reach about 5 m under 4 W effective isotropic radiated power.The whole tag is fabricated in TSMC 0.18μm CMOS technology and the chip size is 880×880μm~2.
This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO 18000-6C protocol. Order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both designed to guarantee the accuracy of the clock under ± 4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 μW with a sensitivity of-9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 μm CMOS technology and the chip size is 880 × 880 μm ~ 2.