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针对过零检测实现的全数字锁相环不仅锁相速度慢,而且过零点的扰动会直接影响锁相精度以及适合模拟电路实现的相干解调技术,在数字电路中实现则需要设计高阶数字低通滤波器,将占用大量数字电路资源并且会显著增加系统功耗等问题,在设计一种新型全数字锁相环(All-digital Enhanced Phase-lock Loop,EPLL)的基础上,结合自适应正交解调技术,提出了一种基于EPLL技术的自适应正交解调技术方案,并对该方案进行了研究与仿真。仿真得到了满意的结果,验证了基于EPLL技术的自适应正交解调技术方案的可行性,并研究验证了算法的参数变化对其性能的影响,为今后算法在数字系统中的实现以及其在各领域的应用研究奠定了坚实的基础。
All-digital phase-locked loop for zero-crossing detection is not only slow phase lock, and zero-crossing disturbance will have a direct impact on the phase-locked accuracy and coherent demodulation technology for analog circuits, digital circuits need to design high-order digital The low-pass filter will occupy a large number of digital circuit resources and will significantly increase the system power consumption and other issues. Based on the design of a new all-digital Enhanced Phase-Lock Loop (EPLL) Orthogonal Demodulation technology, an adaptive quadrature demodulation scheme based on EPLL technology is proposed, and the scheme is studied and simulated. The simulation results are satisfactory. The feasibility of the adaptive quadrature demodulation scheme based on the EPLL technology is verified. The influence of the parameter variation of the algorithm on its performance is verified. The realization of the algorithm in the digital system and its Applied research in various fields has laid a solid foundation.