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本文介绍了中国科学院计算技术研究所研制的功能分布式计算机系统中的GF-10/13模型机及其采用的时钟周期小于10毫微秒的一体化流水线设计技术.并指出了该流水线技术使用的最大延迟差确定时钟周期设计方法在超级计算机及相应的集成电路设计中应用的前景.
This paper introduces the GF-10/13 model machine developed by Institute of Computing Technology, Institute of Computing Technology, Chinese Academy of Sciences, and its integrated pipeline design technology using clock cycles less than 10 ns, and points out that the use of this pipeline technology The maximum delay difference to determine the clock cycle design method in the supercomputer and the corresponding integrated circuit design prospects.