论文部分内容阅读
在综述VLSI结构可测性设计方法的基础上,提出了DSP数据通路基于累加器测试的结构可测性设计方案:利用选择器或三态门实现电路测试、工作模式的切换;在测试模式时,电路中的寄存器复用为扫描链以完成测试矢量的传送从而提高电路的可测试性能.基于本方案的FFT处理器、IIR滤波器、DF-FPDLMS自适应滤波器的数据通路的可测性设计,若忽略数据线延迟,其关键路径仅比原来的分别增加了1、2、0倍的选择器或三态门门延迟.实验表明,若字宽、阶数均为8,它们所需额外硬件开销分别为原来的5.416%、4.969%、4.783%,关键路径分别增加了1.839%、2.382%、0.036%.结果表明,该方案通用性好,扩展性强,额外硬件开销小,几乎不会影响原电路的性能.“,”Approaches of structural design-for-testability are overviewed. Then a scheme of structural design-for- testability for DSP data path to be tested based on accumulation is presented. In the scheme, multiplexers or tristate gates are utilized to switch the modes of the data path between test and work, and some registers in the circuit are reused as scan chains during testing to deliver test patterns to the circuit, and then the circuit testability is improved. Based on the scheme, the data paths of FFT processors, IIR filters and DF-FPDLMS adaptive filters were designed. The critical paths become a little longer and the increased computation times are one, two and zero multiples of the delay of a multiplexer or tristate gate, respectively if the data bus delay is ignored. The experiments of 8-order DSP data paths with 8-bit word width show that the additional hardware overheads are 5.416%, 4.969% and 4.783% of the original circuit hardware overheads, and the critical paths are increased by 1.839%, 2.382% and 0.036% respectively. Results show that the performance of the scheme is good in generality and extension with a little additional hardware overhead and degradation of the original circuit performance.