论文部分内容阅读
本文提出一种数字式锁相环,与常见全数字锁相环比较,具有同步建立时间快与保持时间长的特点。本文着重讨论了建立时间与信噪比的关系,分析了数字环相位误差的传输函数,导出了保持时间的计算公式。指明提高晶体压控振荡器的稳定性,以增加同步保持时间的可能性。最后简要地介绍了实验的结果。
This paper presents a digital phase-locked loop, compared with the common all-digital phase-locked loop, with the establishment of fast synchronization and hold a long time characteristics. This article focuses on the relationship between settling time and signal to noise ratio, analyzes the transfer function of the digital loop phase error, and derives the formula to calculate the hold time. Indicates the possibility of increasing the stability of the crystal VCO to increase the synchronization hold time. Finally, the experimental results are briefly introduced.