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针对MDC架构的FFT处理器中延迟单元使用量较多的情况,介绍了一种存储器矩阵转置切换(Array Transpose Commutator--ATC)方式用以实现FFT处理器数据的存储与切换或抽取功能,与传统的MDC结构相比,可以有效减少延迟单元的使用量。并且介绍了用存储器矩阵实现UWB-OFDM系统的128点FFT处理器的方法。该128点FFT处理器采用基-(8+16)算法,硬件上采用存储器矩阵+并行蝶8运算单元+R16SDF结构,并用硬件描述语言Verilog HDL进行RTL实现,用TSMC 90 nm标准工艺库进行Design Compiler综合,得到芯片内核面积为0.6056mm~2。在52MHz频率下工作可以满足UWB-OFDM系统的要求,内核功耗为5.9mW。在1.2V,25℃条件下,最大工作时钟可达200MHz。整个处理器的控制逻辑简单,数据吞吐率大,能够满足UWB系统的要求。
Aiming at the situation that there are more delay units in FFT processor based on MDC architecture, an Array Transpose Commutator (ATC) method is introduced to store, switch or extract FFT processor data. Compared with the traditional MDC structure, can effectively reduce the delay unit usage. And introduces the method of realizing 128-point FFT processor of UWB-OFDM system by memory matrix. The 128-point FFT processor uses the base- (8 + 16) algorithm, the hardware memory matrix + parallel butterfly 8 + R16SDF structure, and hardware description language Verilog HDL for RTL, TSMC 90 nm standard library for Design Compiler synthesis, the chip core area of 0.6056mm ~ 2. Operating at 52MHz to meet UWB-OFDM system requirements, the core consumes 5.9mW. In 1.2V, 25 ℃ conditions, the maximum working clock up to 200MHz. The entire processor control logic is simple, data throughput, to meet the requirements of UWB system.