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本文介绍一个实用数字集成电路层次式测试图形自动生成(ATPG)系统——FD—Ⅲ。FD—Ⅲ的特点是把测试生成和电路设计结合起来,充分利用电路的层次式结构,借助于电路和功能块已有的测试和模拟结果,加快整个电路的测试生成。该系统能对由WorkView等CAD系统描述的层次式组合电路,同步时序电路进行ATPG。其故障模拟(FS)子系统能对包括异步模块在内的电路进行故障模拟、测试压缩,并给出优化的测试集及其性能指标。目前该系统已对Benchmark等复杂电路和一些实用组合、时序电路进行了测试生成。
This article describes a practical digital integrated circuit level test pattern automatic generation (ATPG) system - FD-Ⅲ. FD-Ⅲ is characterized by the test generation and circuit design combine to take full advantage of the hierarchical structure of the circuit, with the help of the circuit and functional block of the existing test and simulation results to speed up the entire circuit test generation. This system can perform ATPG on the hierarchical combinational circuit described by CAD system such as WorkView and the synchronous timing circuit. Its fault simulation (FS) subsystem can simulate the circuit including the asynchronous module, test the compression, and give the optimized test set and its performance index. At present, the system has Benchmark and other complex circuits and some practical combinations, sequential circuits have been tested to generate.