THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

• 作 者: Deng Xiaoying Yang Jun Shi Lon
• 机 构: National ASIC Systems Engineering Technology Research Center
• 出 处: 电子科学学刊（英文版）
• 发表日期: 2004年期
• 关键词: All-Digital Phase Locked Loop (ADPLL) Digital Controlled Oscillator (DCO) Impuls

A low jitter All-Digital Phase-Locked Loop (ADPLL) used as a clock generator is designed.The Digital-Controlled Oscillator (DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function (ISF) analysis,an effective way is proposed to reduce the ADPLLs jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.8V supply voltage,occupies 0.046mm2 of on-chip area. According to the measured results,the ADPLL can operate from 108MHz to 304MHz,and the peak-to-peak jitter is 139ps when the DCOs output frequency is 188MHz.