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A 19 mW highly integrated GPS receiver with a ΣΔ fractional-N synthesizer is presented in this paper.Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design.A high linearity low noise amplifier(LNA) is integrated into the chip.The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor(CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package.The chip consumes 19 mW(LNA1 excluded) and the LNA1 6.3 mW.Measured performances are:noise figure<2 dB, channel gain=108 dB(LNA1 included), image rejection>36 dB, and-108 dBc/Hz @ 1 MHz phase noise offset from the carrier.The carrier noise ratio(C/N) can reach 41 dB at an input power of-130 dBm.The chip operates over a temperature range of-40, 120 °C and ±5% tolerance over the CMOS technology process.
A 19 mW highly integrated GPS receiver with a ΣΔ fractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier ( LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm × 2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure <2 dB, channel gain = 108 dB (included in LNA1), image rejection> 36 dB, and-108 dBc / Hz @ 1 MHz phase noise offset from the The carrier operates at -30 dBm. The chip operates over a temperature range of -40, 120 ° C and ± 5% tolerance over the CMOS technology process.