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提出了用于无源超高频射频识别(UHF RFID)芯片的射频/模拟前端.该射频/模拟前端通过系统分区和分时供电优化了系统功耗,子电路包括整流电路、基准电路、三轨稳压电路、解调/调制电路、上电复位电路以及时钟电路.通过引入阈值补偿,将全CMOS整流电路的整流效率提升至不低于48%;电流求和型亚阈值基准电路在保证基准精度的同时,有效降低了功耗和芯片面积;无需大尺寸无源器件的解调电路,并从系统架构层面解决了解调失真的问题.该射频/模拟前端电路采用SMIC 0.18μm CMOS工艺库仿真并投片验证,测试结果表明:直流功耗为3.6μA,芯片有效面积为0.27mm2.将该射频/模拟前端电路集成至一款UHF RFID标签芯片中,采用商用阅读器进行测试,其读取距离>6m,平均读取速率达到89.9个/s.
The RF / analog front end for passive UHF RFID chip is proposed.The RF / analog front end optimizes the system power consumption through the system partition and time-sharing power supply.The sub-circuit includes rectifier circuit, reference circuit, tri Rail regulator circuit, demodulation / modulation circuit, power-on reset circuit, and clock circuit. By introducing threshold compensation, the rectification efficiency of the full CMOS rectifier circuit is raised to not less than 48%; the current summing sub-threshold reference circuit is guaranteed While reducing the power consumption and the chip area effectively without the need of a large-scale passive device demodulation circuit and solving the problem of demodulation distortion from the system architecture level.The RF / analog front-end circuit uses the SMIC 0.18μm CMOS Technology Library The simulation results show that the DC power consumption is 3.6μA and the effective area of the chip is 0.27mm2. The RF / analog front-end circuit is integrated into a UHF RFID tag chip and tested with a commercial reader. Take the distance> 6m, the average read rate of 89.9 / s.