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针对带数字校准功能的逐次逼近模/数转换器(SAR ADC),提出将主DAC、校准DAC和基准电压产生电路的电阻串进行复用,从而显著减少了芯片面积,降低了功耗。相比6+6两段电容结构DAC,采用电阻电容混合结构的主DAC和校准DAC节约了37%的版图面积。在0.18μm CMOS工艺下,通过Hspice仿真,SAR ADC的DNL和INL均小于0.4LSB,SNR为75dB。系统正常工作时,总功耗为3.1mW,比不采用电阻串复用的结构减少0.9mW。
For successive approximation analog-to-digital converters (SAR ADCs) with digital calibration functions, it is proposed to multiplex the resistor strings of the main DAC, the calibration DAC and the reference voltage generating circuit, thereby significantly reducing the chip area and reducing the power consumption. Compared to the 6 + 6 two-stage capacitor DAC, the main DAC and the calibration DAC with a resistor-capacitor hybrid structure save 37% of the layout area. The SAR ADC has DNL and INL of less than 0.4LSB and SNR of 75dB through Hspice simulation in a 0.18μm CMOS process. When the system is working normally, the total power consumption is 3.1mW, 0.9mW less than the structure without using the resistor string multiplexing.