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随着集成电路工业的不断发展,集成电路的规模按指数规律的趋势增加,而其输入、输出腿(测试只能通过这些腿)的数量则只按线性规律的趋势增加,这就给测试工作造成极大的困难。一九八二年在第十二届国际容错会议上已经指出:到目前为止,测试所需要的费用超过了设计所需费用,测试所需的时间也超过了设计时间。因此,在线路的设计阶段我们必须考虑它本身的可测试性能。围绕电路可测试性的分析与综合问题,前人作了不少的工作(文献[1]—[7])。尤其是最近提出的可测试性综合问题,使得集成电路的可测试性设计得
With the continuous development of the integrated circuit industry, the trend of the scale of integrated circuits increases exponentially while the number of input and output legs (the test can only pass through these legs) only increases according to the trend of linearity, which gives the test work Cause great difficulties. It has been pointed out at the 12th International Conference on Fault Tolerance in 1982 that so far the cost of testing has exceeded the cost of designing and testing has taken longer than the design time. Therefore, we must consider its own testability during the design phase of the circuit. A great deal of work has been done around the analysis and synthesis of circuit testability (References [1] - [7]). In particular, the recently proposed testability synthesis problem makes the design of the testability of integrated circuits