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为使高性能超标量处理器能够完成多条指令并行,寄存器堆需要提供多端口的高速访问。文章介绍了一种可写穿的16端口寄存器堆存储单元设计,在1.8V0.18μmCMOS工艺下,该存储单元的10个读口和6个写口均可以独立访问。存储单元设计中考虑了紧凑性、可靠性和功耗问题,并且制定了长线规划来减少版图设计中串扰噪声对功能的影响。仿真结果表明,该存储单元可以作为一种更优的实现方法,工作在500MHz主频下的寄存器堆内。
To enable high-performance superscalar processors to complete multiple instructions in parallel, the register file needs to provide multi-port, high-speed access. The article introduces a write-through 16-bit register file memory cell design, the memory cell in the 1.8V0.18μm CMOS process, the read-10 of the storage unit and 6 write ports can be independently accessed. The design of the storage unit takes into account the issues of compactness, reliability and power consumption, and has developed a long-term plan to reduce the effect of crosstalk noise on the layout in layout design. The simulation results show that the memory cell can be used as a better implementation method and work in a register stack with a frequency of 500MHz.