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在分析RFID标签芯片系统架构的基础上,设计了一款适用于超高频射频识别标签芯片的基带控制器,以支持ISO 18000—6Type C标准协议的RFID标签芯片的设计与实现.该基带控制器从系统架构和关键电路设计两个方面进行低功耗的系统集成优化设计,工作主时钟频率采用1.28 MHz,解码电路的采样时钟频率采用2.56MHz,并采用TSMC 0.18μm工艺对面积和功耗进行仿真验证和实现评估.仿真结果标明:该基带控制器符合ISO 18000—6Type C标准协议,芯片面积0.16mm2,芯片功耗20.07μW,能够满足无源射频识别标签芯片的低成本和低功耗的需求.
Based on the analysis of RFID tag chip system architecture, a baseband controller suitable for UHF RFID tag chip is designed to support the design and implementation of RFID tag chip with ISO 18000-6Type C standard protocol. The baseband control From the system architecture and key circuit design, the system integration and optimization of low power consumption are designed. The working clock frequency is 1.28 MHz, the sampling clock frequency of the decoding circuit is 2.56 MHz, and the TSMC 0.18 μm process is adopted for the area and power consumption The simulation results show that the baseband controller complies with ISO 18000-6Type C standard protocol, the chip area is 0.16mm2, and the chip power consumption is 20.07μW, which can meet the low cost and low power consumption of passive radio frequency identification tag chip The demand.