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现代数字通信系统通常采用高阶QAM系统以提高频谱效率,但是采用传统Max-Log-MAP算法的QAM解映射具有很高的实现复杂度。该文采用一种基于Max-LogMAP算法的简化算法,结合QAM星座图对称结构,通过减少比较器和乘法器数量,在FPGA上实现了一种低复杂度的QAM解映射模块,并通过Matlab仿真和FPGA硬件测试验证了所实现的QAM解映射模块的性能。测试结果证明,利用简化算法实现的QAM解映射模块与传统MaxLog-MAP解映射模块相比具有相同的吞吐率和误码性能,且能有效减少QAM解映射模块的硬件资源。
Modern digital communication systems usually adopt high-order QAM system to improve the spectral efficiency, but the QAM de-mapping using the traditional Max-Log-MAP algorithm has a very high implementation complexity. In this paper, a simplified algorithm based on Max-LogMAP algorithm is used in combination with QAM constellation symmetric structure. By reducing the number of comparators and multipliers, a low complexity QAM de-mapping module is implemented in FPGA, And FPGA hardware test to verify the performance of the QAM demapping module. The test results show that the QAM demapping module realized by the simplified algorithm has the same throughput and error performance compared with the traditional MaxLog-MAP demapping module, and can effectively reduce the hardware resources of the QAM demapping module.