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A novel low-power DC offset calibration(DCOC) method independent of intermediate frequency(IF) gain for zero-IF receiver applications has been reported. The conventional analog DCOC method consumes greater power and affects the performance of the receiver. The conventional mixed-signal method requires enhanced memory to store the calibration results at different receiver gains as the DC offset is relative to the radio frequency(RF) and IF gain. A novel algorithm is presented to make the DCOC process independent of IF gain, which significantly reduces the memory area. With the proposed circuit, the receiver calibrates only once so settle-time and power consumption of the IF circuit is lowered. A DCOC circuit with the proposed method is manufactured in 0.18 μm CMOS technology that drains nearly 0 mA equivalent current from a 1.8 V power supply.
A novel low-power DC offset calibration (DCOC) method independent of intermediate frequency (IF) gain for zero-IF receiver applications has been reported. The conventional analog DCOC method consumes greater power and affects the performance of the receiver. signal method requires enhanced memory to store the calibration results at different receiver gains as the DC offset is relative to the radio frequency (RF) and IF gain. A novel algorithm is presented to make the DCOC process independent of IF gain, which significantly reduces the A DCOC circuit with the proposed method is manufactured in 0.18 μm CMOS technology that drains nearly 0 mA equivalent current from a 1.8 V power supply.