Register Allocation Algorithm for High-Level Circuit Synthesis for Improved Testability

• 作 者: CHENG Benmao WANG Hong YANG Sh
• 机 构: Qingdao Branch, Naval Aeronautical Engineering Academy, Qingdao 266041, China“,”Department of Automa
• 出 处: 黑龙江科技学院学报
• 发表日期: 2004年期
• 关键词: high-level synthesis (HLS) register allocation testability weighted graph

Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desatu-ration algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits. Tests on some benchmarks show that the algorithm gives a higher fault coverage than other algorithms with less area overhead and even less time delay.