2.5GHz CMOS高速双模前置分频器设计

• 作 者: 杨文荣 曹家麟 冉峰 王键
• 机 构: Microelectronic Research and Development Center, Shanghai University, Shanghai 200072, P.R. China
• 出 处: 上海大学学报（英文版）
• 发表日期: 2004年3期
• 关键词: CMOS prescaler source-coupled logic(SCL) phase-locked loop(PLL)

A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3. 2 GHz. Running at 2. 5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.