论文部分内容阅读
介绍在等离子工艺中的等离子充电损伤,并且利用相应的反应离子刻蚀(RIE)Al的工艺试验来研究在nMOSFET器件中的性能退化。通过分析天线比(AR)从100:1到10000:1的nMOSFET器件的栅隧穿漏电流,阈值Vt漂移,亚阈值特性来研究由Al刻蚀工艺导致的损伤。试验结果表明在阈值Vt漂移中没有发现与天线尺寸相关的损伤,而在栅隧穿漏电流和低源漏电场下亚阈值特性中发现了不同天线比的nMOS器件有相应的等离子充电损伤。在现有的理解上对在RIEAl中nMOS器件等离子充电损伤进行了讨论,并且基于这次试验结果对减小等离子损伤提出了一些建议。
The plasma charge damage in a plasma process is introduced and the process degradation in the nMOSFET device is investigated using a process experiment of reactive ion etching (RIE) Al. The damage caused by the Al etching process was investigated by analyzing the gate tunneling leakage current, the threshold Vt drift, the subthreshold characteristics of an nMOSFET device with an antenna ratio (AR) from 100: 1 to 10000: 1. The experimental results show that no antenna size-related damage is found in the Vt drift of the threshold, whereas the plasma damage of the nMOS devices with different antenna ratios is found in the subthreshold characteristics of gate tunneling leakage current and low source / drain field. In the current understanding, the plasma damage of nMOS devices in RIEAl is discussed, and based on the results of this experiment, some suggestions for reducing plasma damage are proposed.