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基于直流电流电压(DCIV)理论和界面陷阱能级U型对称分布模型,可以获取硅界面陷阱在禁带中的分布,即利用沟道界面陷阱引起的界面复合电流与不同源/漏-体正偏电压(Vpn)的函数关系,求出对应每个Vpn的有效界面陷阱面密度(Neff),通过Neff函数与求出的每个Neff值作最小二乘拟合,将拟合参数代入界面陷阱能级密度(DIT)函数式,作出DIT的本征分布图。分别对部分耗尽的n MOS/SOI和p MOS/SOI器件进行测试,得到了预期的界面复合电流曲线,并给出了器件界面陷阱能级密度的U型分布图。结果表明,两种器件在禁带中央附近的陷阱能级密度量级均为109cm-2·e V-1,而远离禁带中央的陷阱能级密度量级为1011cm-2·e V-1。
Based on the DCIV theory and U-shaped symmetry distribution model of interface trap level, the distribution of silicon interface traps in the forbidden band can be obtained, that is, the interface recombination current caused by channel interface traps and the source / drain- (Vpn), find the effective surface trap density (Neff) corresponding to each Vpn, perform a least-squares fit on each Neff value obtained by the Neff function, and assign the fitting parameters to the interface traps Energy Density (DIT) function formula, to make the DIT of the intrinsic distribution. The partially depleted n MOS / SOI and p MOS / SOI devices were tested respectively. The expected interfacial composite current curves were obtained, and the U-shaped distributions of device interface trap level densities were given. The results show that both devices have a trap level density of 109cm-2 · e V-1 near the center of the forbidden band and a trap level density of 1011cm-2 · e V-1 away from the center of the forbidden band .