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一、概述本文介绍一种新型数字摄象机专用低功耗MPEG-2视频CODEC(Coder和Decoder的缩写,即编码和解码)LSI。该电路具有编码和解码及摄象机要求的其他功能(如高分辨率静止图象的编码和逐行帧编码等)。该LSI利用0.18μm CMOS技术制造工艺,在8.25 mm×8.25mm的硅片上集成4M个晶体管(770K位门电路和180K位SRAM),并在54 MHz时钟频率上正常运行。为了实现低电压、低功耗(500 mW)工作及方便外围电路供电,其芯片和I/O供电电压是不同的,前者为1.8 V,后者为3.3 V。216引脚采用CSP封装。208引脚采用QFP封装。
I. Overview This article describes a new type of digital camera dedicated low-power MPEG-2 video CODEC (Coder and Decoder abbreviation, that is, encoding and decoding) LSI. The circuit has other functions such as encoding and decoding and camera requirements (such as high resolution still image encoding and progressive frame encoding, etc.). The LSI uses 0.18μm CMOS technology to fabricate a process that integrates 4M transistors (770K gates and 180K-bit SRAM) on an 8.25 mm × 8.25mm silicon and operates normally at a 54 MHz clock frequency. For low-voltage, low-power (500 mW) operation and peripheral circuitry, the chip and I / O supply voltages are different, with 1.8 V for the former and 3.3 V for the latter. 216-pin CSP package. 208 pin QFP package.