论文部分内容阅读
引言如今,人们已经能够将大型RC网络直接布设在高分辨率Δ∑模数转换器之前,同时又不会使它们的DC准确度发生任何劣化(见图1)。LTC(?)248x系列转换器利用EasyDriveTM技术(这是一种能够自动消除差分输入电流的全无源采样网络)来解决了这问题。EasyDrive技术并未采用会导致性能下降的片内缓冲器(请参见“为什么不采用片内缓冲器?”),而是采用了一种新型架构,这种架构能够在采用元件值高达100kΩ和10μF的输入RC网络的情况下维持0.002%的全标度误差。与先前的Δ∑ADC世代相比,该新技术提供了众多的优点:·轨至轨共模输入范围·高阻抗传感器的直接数字化·消除了ADC输入引脚所承受的采样脉冲尖峰·简单的外部低通滤波处理·噪声/功耗的减少·消除了外部RC稳定误差·至外部放大器的简易型连接·消除了传输线对远端传感器的影响工作原理Δ∑转换器通过将多个低分辨率转换整合成一个高分辨率结果来实现高分辨率。市面上现售的大多数Δ∑转换器都是将数百甚至数千个1位转换组合成为单个16、20或24位结果。这种做法明显的优点是实现一个1位转换器要比实现一个24位转换器容易得多。为了获得高分辨率,在转换周期中需对输入进行多次采样。问题在于Δ∑转换器的输入结构是一个开关电容器网络。电容器被作为最终输出代码的一个函数而在输入、基准和地之间进行快速转换(频率高达10MHz)。每次这些电容器被转换至ADC输入,产生了一个电流脉冲。ADC的输入引脚将承受一种充电/放电脉冲图形。该图形是输入和基准电压的一个复函数。在每个采样周期中未能完全稳定的外部RC网络会导致很大的DC误差。解决该问题的巧妙之处在于利用了Δ∑转换器的过采样特性。基于每个采样的前端电容器开关操作与传统的Δ∑转换器采样是等同的。一种创新的前端采样架构可控制电容器阵列的开关操作模式。当在整个转换周期中进行加法运算时,总差分输入电流为零,这与差分输入电压、共模输入电压、基准电压或输出代码无关。共模输入电流是恒定的,并与输入共模电压和基准共模电压两者之差成比例。
Introduction Today, large RC networks have been deployed directly to high-resolution delta-sigma ADCs without any degradation in their DC accuracy (see Figure 1). The LTC (?) 248x Series converter addresses this issue with EasyDriveTM technology, an all-passive sampling network that automatically eliminates differential input current. Instead of using an on-chip buffer (see “Why not use an on-chip buffer?”) That causes performance degradation, the EasyDrive technology incorporates a new architecture that uses components with values up to 100kΩ and 10μF Of the input RC network maintains a 0.002% full scale error. The new technology offers many advantages over the previous ΔΣADC generation: · Rail-to-rail common mode input range · Direct digitalization of high-impedance sensors · Eliminates sample pulse spikes on the ADC input pins · Simple External low-pass filtering · Reduction of noise / power consumption · Elimination of external RC settling error · Simple connection to external amplifier · Elimination of the effect of transmission line on the remote sensor. Operation Principle The delta-sigma converter converts a low-resolution Converting to a high-resolution result to achieve high resolution. Most delta-sigma converters on the market today combine hundreds or even thousands of 1-bit conversions into a single 16, 20 or 24 bit result. The obvious advantage of this approach is that it is much easier to implement a 1-bit converter than to implement a 24-bit converter. In order to obtain high resolution, the input needs to be sampled multiple times during the conversion cycle. The problem is that the delta sigma converter’s input structure is a switched capacitor network. The capacitor is quickly converted between inputs, references and ground (up to 10MHz) as a function of the final output code. Each time these capacitors are converted to the ADC input, a current pulse is generated. The ADC input pins will be subjected to a charge / discharge pulse pattern. This graph is a complex function of the input and reference voltage. An external RC network that fails to fully stabilize during each sampling period can result in a large DC error. The trick to solve this problem is to take advantage of the delta-sigma converter’s oversampling properties. The front end capacitor switching operation based on each sample is equivalent to the traditional delta sigma converter sample. An innovative front-end sampling architecture controls the switching mode of operation of the capacitor array. When added during the entire conversion cycle, the total differential input current is zero regardless of the differential input voltage, common-mode input voltage, reference voltage, or output code. The common mode input current is constant and proportional to the difference between the input common mode voltage and the reference common mode voltage.