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用 0 .35μm、一层多晶、四层金属、3.3V的标准全数字 CMOS工艺设计了一个全集成的 2 .5 GHz L C VCO,电路采用全差分互补负跨导结构以降低电路功耗和减少器件 1/ f噪声的影响 .为了减少高频噪声的影响 ,采用了在片 L C滤波技术 .可变电容采用增强型 MOS可变电容 ,取得了 2 3%的频率调节范围 .采用单个 16边形的对称片上螺旋电感 ,并在电感下加接地屏蔽层 ,从而减少芯片面积 ,优化 Q值 .取得了在离中心频率 1MHz处 - 118d Bc/ Hz的相位噪声性能 .电源电压为 3.3V时的功耗为 4 m A.
A fully integrated 2.5 GHz LC VCO is designed with 0 .35μm, single-layer polycrystalline, four-metal, and 3.3V standard all-digital CMOS technology. The circuit uses a fully-differential complementary negative transconductance structure to reduce circuit power consumption and Reduce the impact of device 1 / f noise. In order to reduce the impact of high-frequency noise, using the chip LC filter technology. Variable capacitance using enhanced MOS variable capacitance, made 23% of the frequency adjustment range. With a single 16-edge Shaped symmetric on-chip spiral inductor with a ground shield added to the inductor to reduce chip area and optimize Q. The phase noise performance was achieved at 1 MHz from the center frequency - 118 dBc / Hz. At a supply voltage of 3.3 V The power consumption is 4 m A.