Dynamically reconfigurable architecture for symmetric ciphers

• 作 者: Bo WANG Leibo LIU
• 机 构: National Laboratory for Information Science and Technology, Tsinghua University,
• 出 处: Science China(Information Sciences)
• 发表日期: 2016年04期
• 关键词: symmetric throughput overhead cryptographic processor hierarchical cipher operat

In this paper, a very large scale integration(VLSI) architecture for a reconfigurable cryptographic processor is presented. Several optimization methods have been introduced into the design process. The interconnection tree between rows(ICTR) method reduces the interconnection complexity and results in a small area overhead. The hierarchical context organization(HCO) scheme reduces the total context size and increases the dynamic configuration speed. Most symmetric ciphers, including AES, DES, SHACAL-1, SMS4, and ZUC, can be implemented using the proposed architecture. Experimental results show that the proposed architecture has obvious advantages over current state-of-the-art architectures reported in the literature in terms of performance,area efficiency(throughput/area) and energy efficiency(throughput/power).

Several optimization methods have been introduced into the design process. The interconnection tree between rows (ICTR) method reduces the interconnection complexity and results in a small The overhead context organization (HCO) scheme reduces the total context size and increases the dynamic configuration speed. Most symmetric ciphers, including AES, DES, SHACAL-1, SMS4, and ZUC, can be implemented using the proposed architecture. Experimental results show that that proposed architecture has clearly advantages over current state-of-the-art architectures reported in the literature in terms of performance, area efficiency (throughput / area) and energy efficiency (throughput / power).