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Recent years,the hardening of combinational circuits is becoming a common concern.Unlike the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)sensitivity.The mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits.
Recent years, the hardening of combinational circuits is becoming a common concern. Uni-the transistor-level hardening technique, the cell-level hardening technique, a divide and conquer strategy, can make some use character of the cell-circuit module to mitigate single event transient (SET) sensitivity.The mirror image (MI) technique proposed in this paper can be robustly enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process, the results that that MI technique can reduce reduce the SET pulse width from the anterior-stage PMOS over 25%, and can mitigate the SET pulse width from the posterior-stage PMOS about 10%. The MI technique, a representation of the cell-level technique, may be the future of the hardening of combinational circuits.