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In this paper, an Ethernet controller SoC solution and its low power design for testability (DFT) for information appli- ances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit (MCU), media access control (MAC) circuit and embedded memories such as static random access memory (SRAM), read only memory (ROM) and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits: the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is em- ployed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test (BIST). By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconduc- tor (CMOS) technology, the die area is 4.8×4.6 mm2. Test results show that the maximum throughput of Ethernet packets may reach 7 Mb·s-1.
In this paper, an Ethernet controller SoC solution and its low power design for testability (DFT) for information appli- ances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit (MCU) (MAC) circuit and embedded memories such as static random access memory (SRAM), read only memory (ROM) and flash are all integrated together. At order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits: the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is em-ployed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test (BIST). By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by 0.25 μm two-poly four-metal mixed signal complementary metal oxide semicon duc-tor (CMOS) technology, the die area is 4.8 × 4.6 mm2. Test results show that the maximum throughput of Ethernet packets may reach 7 Mb · s-1.