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前言ECL 电路具有“线或”能力,因此也能直接连接成数据总线形式,即可以把许多输出和输入接到同一根传输线上如图1所示。数据总线与“线或”不一样,任何时候只允许一个驱动器输出处于高电平而其它输出必须处于低电平,并且所有输入和处于低电平的输出都要作为传输线的电容负载,一般10K 电路一个处于低电平的输出电容约为2pf。由于电容负载的影响,将使线阻抗下降,传输延迟增加。同时每一个接点都是阻抗不连续点,因此在传输过程中信号每经过一个节点都会发生反射,当节点增多时反射
Introduction ECL circuits are “wired or” capable and therefore can also be connected directly to the data bus, meaning that many outputs and inputs can be connected to the same transmission line as shown in Figure 1. The data bus is not the same as a “wire or”. Only one driver output is allowed to go high and the other outputs must be low at any time, and all inputs and outputs at low level are used as capacitive loads on the transmission line, typically 10K The circuit is a low level of output capacitance of about 2pf. Due to the influence of the capacitive load, the impedance of the wire will decrease, and the transmission delay will increase. At the same time, each contact is a discontinuous point of impedance, so the signal will be reflected by each node during the transmission. When the number of nodes increases, the reflection