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This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC’s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm~2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.
This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC’s 0.13 μm CMOS technology. The active area of the transceiver is 0.016 mm ~ 2 and it consumes a total of 150 mW power at a 1.2 V supply voltage. The transmitter uses two stage pre-emphasis circuits with active inductors, reducing inter-symbol interference and extended bandwidth; the receiver uses a time-domain adaptive equalizer, the circuit uses an inductive peaking technique and extends the bandwidth, and the use of active inductors reduces the circuit area and power consumption effectively. The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps, the output signal swing of the transmitter is 350 mV with jitter of 14 ps, the eye opening of the receiver is 135 mV and the eye width is 0.56 UI. The circuit performance meets meets the requirements of the PCI-Express 2.0 protocol.