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使用化学机械抛光(CMP)的方式,对商用芯片进行拆解,获得了不同制造工艺的铜/低k介质互连结构样品。通过对所获得的32 nm制造工艺的铜/低k介质互连结构样品进行进一步的化学机械抛光实验来研究抛光过程中出现的损伤。实验结果发现,抛光压力过大和过小分别会造成宏观缺陷和导线腐蚀,互连线的分布会导致导线自身的碟型缺陷、不同图案布线结构交界两侧明显的表面高度差异以及同一图案布线结构内部的表面周期性高度起伏。这种表面高度差异可以通过预补偿的方式得到一定的改善。
Using chemical mechanical polishing (CMP) approach, commercial chips were disassembled to obtain copper / low-k dielectric interconnection samples with different manufacturing processes. The damage occurred in the polishing process was investigated by further chemical-mechanical polishing experiments on the obtained copper / low-k dielectric interconnection samples of 32 nm fabrication process. The experimental results show that the polishing pressure is too large and too small will cause macroscopic defects and lead corrosion respectively. The distribution of interconnection leads to the disc defect of the lead itself. The obvious surface height difference between the two sides of the intersection of different pattern wiring structure and the same pattern wiring structure The internal surface of the periodic ups and downs. This surface height difference can be pre-compensated way to get some improvement.