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本文论述了一种功能易测的可编程逻辑阵列(PLA)的设计方案,依靠增加一部分附加逻辑及适当设置少量的测试点,使PLA成为可“分而治之”的易测器件.只需少量的测试次数就可测定其全部的逻辑“编程点”。文中所述的测试算法不仅能验证PLA的拓朴结构.而且也能检测包括附加逻辑电路在内的各种逻辑故障.此易测方案所需增加的芯片面积和引线数较少.测试集与PLA逻辑功能基本无关.对于具有n个输入、p条字线的PLA片子.其测试量约为p(2n+1)。文中还对方案作了某些深入的讨论.
This article discusses a design scheme of a programmable logic array (PLA) that is easy to test and functional, and relies on additional logic and the proper setting of a small number of test points to make the PLA a “testable” testable device. The number of times can be measured all of its logic “programming point.” The test algorithm described in this article not only verifies the topology of the PLA but also detects various logic faults, including additional logic, which requires less chip area and fewer leads. The PLA logic has little to do with PLA slices with n inputs and p word lines, measuring about p (2n + 1). The article also made some in-depth discussion of the program.