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This paper presents an analog front end for a power line communication system,including a 12-bit3.2-MS/s energy-efficient successive approximation register analog-to-digital converter,a positive feedback programmable gain amplifier,a 9.8 ppm/°C bandgap reference and on-chip low-output voltage regulators.A two segment capacitive array structure(6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements.Implemented in the GSMC 0.13μm 1.5 V/12 V dual-gate 4P6 M e-flash process,the analog front end occupies an area of 0.457 mm2 and consumes power of18.8 m W,in which 1.1 m W cost by the SAR ADC.Measured at 500 k Hz input,the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 d B and 60.60 d B respectively,achieving a figure of merit of 350 f J/conversion-step.
This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS / s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm / ° C bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure (6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 μm 1.5 V / 12 V dual-gate 4P6 M e-flash process, the analog front end occupies an area of 0.457 mm 2 and consumes power of 18.8 m W, where 1.1 m W cost by the SAR ADC. Measured at 500 k Hz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 d B and 60.60 d B respectively, achieving a figure of merit of 350 f J / conversion-step.