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提出了一种新的时钟性能驱动的增量式布局算法 ,它针对目前工业界较为流行的标准单元布局 ,应用查找表模型来计算延迟 .由于在布局阶段较早地考虑到时钟信息 ,可以通过调整单元位置 ,更有利于后续的有用偏差时钟布线和偏差优化问题 .来自于工业界的测试用例结果表明 ,该算法可以有效地改善合理偏差范围的分布 ,而对电路的其它性能影响很小
A new clock performance-driven incremental layout algorithm is proposed, which is based on the standard cell layout that is popular in the industry and uses a look-up table model to calculate the delay.Because the clock information is considered earlier in the layout stage, Adjusting the location of the cell is more conducive to the follow-up of the useful deviation clock routing and bias optimization problems.Experimental results from the industry show that the algorithm can effectively improve the distribution of the reasonable deviation range, and has little effect on the other performance of the circuit