论文部分内容阅读
介绍了VHDL语言及其基本特点和VHDL强大的仿真工具Active VHDL ,并结合例子描述了VHDL语言在数字电路设计仿真调试阶段所起的重要作用 ,仿真通过之后需要进行综合才能完成设计工作。结合使用VHDL的仿真和综合工具进行电子设计自动化设计的实际芯片取得了令人满意的结果。
Introduced the VHDL language and its basic features and VHDL powerful simulation tool Active VHDL, and combined with examples described VHDL language in the digital circuit design simulation debugging phase plays an important role, the simulation needs to be integrated to complete the design work. The actual chip that uses the VHDL simulation and synthesis tool to carry on the electronic design automation design has obtained the satisfactory result.