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Silicone Laboratories 公司开t发成功一种通信交换机端口卡使用的时钟倍频器，通常与其他时钟器件一起构成完全的CMOS设计。数字锁相环(PLL)是倍频器的核心，它采用与该公司的时钟和恢复电路同样的基本设计，获得小于0.7ps的抖动。倍频器可提供达到622MHz的四组输出
Silicone Laboratories Inc. succeeded in developing a clock multiplier for use with a communications switch port card, often along with other clock devices to make a complete CMOS design. The Digital Phase-Locked Loop (PLL) is the core of the multiplier and achieves less than 0.7ps jitter using the same basic design as the company’s clock and recovery circuitry. The frequency multiplier provides four sets of outputs up to 622MHz