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随着工艺节点的不断降低,存储器的软错误率呈指数趋势上升,容错技术已成为存储器设计中的重要环节。依据美国NASA Rosetta实验数据,对错误检纠错码(EDAC:Error Detection and Correction)和不同的在线刷新模式组成的多种容错方案进行可靠性建模与量化评估,提出了不同工艺节点下嵌入式存储器容错技术选择的判据方法。在地面单粒子模拟实验中进行验证,结果表明,该方法预测的失效率评估结果与实验测试结果的平均偏差约为10.3%。
As the number of process nodes decreases, the soft error rate of memory shows an exponential trend. Fault-tolerant technology has become an important part of memory design. According to the NASA Rosetta experimental data from the United States, reliability modeling and quantitative assessment of various fault tolerance schemes composed of EDAC (Error Detection and Correction) and different online refresh modes are carried out. The embedded technologies of different process nodes Criterion Method of Memory Fault Tolerance Technology Selection. The simulation results show that the average deviation between the predicted failure rate and the experimental test results is about 10.3%.