利用降维图简化逻辑函数

• 作 者: 谭迎宾
• 出 处: 电子技术应用
• 发表日期: 1984年04期
• 关键词: 逻辑函数 降维 卡诺图 最小项 逻辑设计 时序电路 公因子 二步 变量 量数

在1978年出版的“Digital Circuits and LogicDesign”一书中,作者Samoel C.Lee介绍用SM图方法设计时序电路时,提出了降维图这一重要工具。在该方法中,降维图代替了卡诺图,从而使逻辑设计大为简化。降维图初露头角,就显示出了它简单而又实用的特点。在逻辑设计中,常常利用卡诺图简化逻辑函数。如所熟知,当变量数不大于四时,这是行之有效的。

In his book, Digital Circuits and LogicDesign, published in 1978, author Samoel C. Lee introduced the important tool for dimensionality reduction when designing sequential circuits using the SM graph approach. In this method, the dimensionality reduction replaces the karnaugh map, which simplifies the logic design. Reduced-dimensional map to appear on the table, it shows its simple and practical features. In logic design, Karnaugh map is often used to simplify logic functions. As is well known, this works well when the number of variables is not greater than four.