RESEARCH OF FAST MODULAR MULTIPLIER FOR A CLASS OF FINITE FIELDS

• 作 者: Jin Yi Shen Haibin Chen Huafen
• 机 构: Institute of VLSI design
• 出 处: 电子科学学刊（英文版）
• 发表日期: 2004年期
• 关键词: Fast modular multiplication Bit-parallel multiplier Trinomials
• 基金项目: 国家高技术研究发展计划(863计划)

A new structure of bit-parallel Polynomial Basis (PB) multiplier is proposed, which is based on a fast modular reduction method. The method was recommended by the National Institute of Standards and Technology (NIST). It takes advantage of the characteristics of irreducible polyno- mial, i.e., the degree of the second item of irreducible polynomial is far less than the degree of the polynomial in the finite fields GF(2