Implementation of encoder and decoder for LDPC codes based on FPGA

• 作 者: CHENG Kun SHEN Qi LIAO Shengka
• 机 构: DepartmentofModernPhysics,ShanghaiBranch,ChineseAcademyofSciencesCenterforExcellenceandSynergeticInn
• 出 处: 系统工程与电子技术:英文版
• 发表日期: 2019年4期
• 关键词: LOW-DENSITY parity-check(LDPC) field PROGRAMMABLE gate array(FPGA) normalized mi
• 基金项目: the National Natural Science Foundation of China(11705191),the Anhui Provincial Natural Science Foundation(1808085QF180),the Natural Science Foundation of Shanghai(18ZR1443600).

This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-