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随着微电子技术的发展，单个芯片可以集成越来越多的晶体管。目前的预测是，在未来的十五年，十亿晶体管可以做在一个芯片上。如何充分利用这巨大的资源，计算机体系结构设计者纷纷提出了许多建议。本文在探讨处理机体系结构发展过程的基础上，提出了一种新的＂并行多线程体系结构—ＰＭＡ＂。ＰＭＡ的主要想法是把多个逻辑处理机集成在同一芯片上，而且多个执行部件由这些逻辑处理机所共享。在每个周期，处理机从多个线程取出多条指令调度执行。与简单的单片多处理机相比，它提高了执行部件的利用效率。另一个特点便是ＰＡＭ同时支持指令级和线程级的并行操作。在描述了ＰＭＡ的基本原理之后，本文给出了一种可能的ＰＭＡ硬件实现方案，并且讨论了对软件支持ＰＭＡ所提出的新的要求。
With the development of microelectronics, a single chip can integrate more and more transistors. The current forecast is that in the next fifteen years, billions of transistors can be made on a single chip. How to make full use of this huge resources, computer architecture designers have put forward many suggestions. Based on the development of processor architecture, this paper proposes a new parallel multi-threaded architecture (PMA). The main idea of PMA is to integrate multiple logic processors on the same chip, and multiple execution components are shared by these logic processors. In each cycle, the processor fetches multiple instructions from multiple threads to schedule execution. It improves the utilization of executive components compared to simple monolithic multiprocessors. Another feature is that PAM supports both parallel instruction-level and thread-level operations. After describing the basic principles of PMA, this paper presents a possible PMA hardware implementation and discusses the new requirements for software support for PMA.