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传统上,对于通信系统内接口应用使用的现场可编程门阵列(FPGA)的讨论,多集中于原始的I/O速度。遗憾地,人们通常忽略FPGA如何处理上载至“芯片上”的高速数据。许多FPGA架构并不能妥善地处理庞大的数据流,造成大部分情况均出现瓶颈现象。最终,这种瓶颈迫使设计者考虑采用价格昂贵的方案,以便利用传统的FPGA达至性能指标。要使FPGA被视作下一代高速通信应用的可行解决方案,我们需要一种新的FPGA架构,经过优化以消除这种瓶颈问题。
Traditionally, the discussion of field programmable gate arrays (FPGAs) used for interfacing applications in communications systems has focused more on the original I / O speed. Unfortunately, one often overlooks how FPGAs handle high-speed data that is uploaded to “on-chip.” Many FPGA architectures do not properly handle large data flows, causing bottlenecks in most cases. Ultimately, this bottleneck forces designers to consider expensive solutions that can be used to achieve performance metrics using traditional FPGAs. To make FPGAs a viable solution for next-generation high-speed communications applications, we needed a new FPGA fabric that was optimized to eliminate this bottleneck.