Efficient and Low-Latency Systolic Array Architecture for Full Searches in Block-Matching Motion E

• 作 者: 张武健 陈弘毅
• 出 处: Tsinghua Science and Technology
• 发表日期: 2001年04期
• 关键词: latency pixel broadcasting pipeline matching sequentially bandwidth deliver abso

This paper describes an efficient, low latency systolic array architecture for full searches in block matching motion estimation. Conventional one dimensional systolic array architecture is used to develop a novel ring like systolic array architecture through operator rescheduling considering the symmetry of the data flow. High latency delay due to stuffing of the array pipeline in the conventional architecture was eliminated. The new architecture delivers a higher throughput rate, achieves higher processor utilization, and has low power consumption. In addition, the minimum memory bandwidth of the conventional architecture is preserved. 

This paper describes an efficient, low latency systolic array architecture for full searches in block matching motion estimation. Conventional one dimensional systolic array architecture is used to develop a novel ring like systolic array architecture through operator rescheduling considering the symmetry of the data flow. delay due to stuffing of the array pipeline in the conventional architecture was eliminated. The new architecture delivers a higher throughput rate, achieves higher processor utilization, and has low power consumption.