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在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。
The leakage of traditional electrostatic discharge protection (ESD) power clamp circuits has an increasing impact on the IC chip after it reaches the nano-scale process. In order to reduce the electric leakage, a new low-leakage ESD power supply clamp circuit is designed. The clamp circuit reduces the voltage difference across the MOS capacitor by feedback forming by two MOS tubes with the smallest size. The simulation results show that the leakage current of this clamp circuit is only 32.59nA under the same conditions, which is two orders of magnitude lower than the traditional clamp circuit. Under ESD pulse, the new ESD clamp circuit is equivalent to the traditional circuit, the ESD device is effectively turned on.