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芯片以脉冲激发神经网络算法为原型设计,遵循生物神经元的脉冲时序依赖可塑性学习规则。它具有256个神经元,64K(256×256)个2进制突触,神经元承担运算,相当于CPU,突触由SRAM组成,相当于神经网络的连接权重矩阵。CPU与SRAM高度整合,省略了通信总线。芯片的核心电路面积仅0.0025mm2。芯片不需要编程,通过配置参数可以执行多种神经网络算法。芯片的研发依赖于这几个方面:生物神经元的学习规律;由此导出的神经网络算法;CMOS材料和工艺;SRAM和CPU的电路设计。
The chip uses a pulse-excited neural network algorithm as the prototype design, following the pulse neuron’s pulse timing dependency on plasticity learning rules. It has 256 neurons, 64K (256 × 256) binary synapses, neurons undertake the operation, equivalent to the CPU, the synapses by the SRAM, equivalent to the neural network connection weight matrix. CPU and SRAM highly integrated, omit the communication bus. The core circuit area of the chip is only 0.0025mm2. The chip does not need programming, through the configuration parameters can perform a variety of neural network algorithms. Chip research and development depends on these aspects: the learning rules of biological neurons; the resulting neural network algorithm; CMOS materials and processes; SRAM and CPU circuit design.