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要提高数据处理机的处理能力,就要提高所用元件的性能。在最新的计算机中,中央处理器(CPU)中已使用亚毫微秒逻辑元件。但是为直接对应于从这样高速的CPU 中取数,不能说缓冲存储器原来的几十毫微秒的速度就够了。作者从上述背景提出研制取数时间小于10ns、每芯片1K 位的超高速大容量缓冲存储器用的器件。这次,完成了电路设计,试制了存储器。本文扼要地介绍了试制存储器的设计和特性1 研制的目标和存储器的组成图1为公开发表的,并具有代表性的MOS和双极半导体存储器的取数时间与功耗的关系。同时,也给出了要试制存储器的性能的目
To improve the data processor processing power, it is necessary to improve the performance of the components used. In the latest computers, sub-nanosecond logic elements have been used in the central processing unit (CPU). But in order to directly correspond to taking such a high speed from the CPU, can not say that the buffer memory speed of the original tens of nanoseconds is enough. From the above background, the author proposes to develop a device for an ultra-high-speed large-capacity buffer memory with a sampling time of less than 10ns and a bit of 1K per chip. This time, completed the circuit design, trial production of memory. This article briefly introduces the design and characteristics of a prototype memory. 1 Development of the target and memory components Figure 1 shows the published and representative MOS and bipolar semiconductor memory access time and power consumption. At the same time, it also gives the purpose of trying out the performance of memory