论文部分内容阅读
In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, high-speed flash analog-to-digital converters (ADCs). In [1], we theoretically describ the calibration technique and perform a behavioral-level simulation to test its functionality [1]. In this work, we discuss some issues in transistor-level implementation. The predominant factors that contribute to static errors such as reference generator mismatch and track-and-hold (T/H) gain error can be treated as input-referred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistor-level implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.
In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, high-speed flash analog-to-digital converters (ADCs). In [1], we theoretically describ the calibration technique and perform a behavioral-level simulation to test its functionality [1]. The predominant factors that contribute to static errors such as reference generator mismatch and track-and-hold (T / H) gain error can be treated as input-referred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistor-level implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.