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目前的集成注入逻辑(I~2L)结构显示出高组装密度和极好的速度功耗乘积,这是将横向pnp晶体管和反向运用的多收集极npn晶体管结合起来实现的。此外,采用标准双极工艺的优点导致集成注入逻辑技术广泛用于大规模集成电路领域。但是用这些常规工艺实现的集成注入逻辑电路严重限制高速度应用,在实际的LSI电路中,一般I~2L门的最小传输延迟时间大约为40～100ns,这比高速电路,例如:TTL大得多。
Current integrated injection logic (I ~ 2L) structures exhibit a high packing density and an excellent speed power product by combining a lateral pnp transistor with a reverse-acting multi-collector npn transistor. In addition, the benefits of using standard bipolar processes have led to the widespread use of integrated injection logic technology in the area of large scale integrated circuits. However, the integrated logic injection logic implemented with these conventional technologies severely limits high-speed applications. In a real LSI circuit, a typical I ~ 2L gate has a minimum transfer delay of about 40~100ns, which is higher than that of a high-speed circuit such as TTL many.