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在半导体器件制造中,一般说来,半导体晶体中的位错过多,会使器件性能变坏,这是由于位错提供了杂质沉积的核心,从而造成微等离子击穿,使p-n结反向击穿特性变软,漏电流显著增加,严重时还会形成p-n结上的漏电沟道使器件报废;位错线上的杂质增强扩散,还会形成浅结时的E-C管道;在一般情形下,也会形成基区陷落效应;位错还是噪声源……。凡此种种,都是器件制造者不希望的。所以,制备低位错的外延片对于提高器件的性能是非常必要的。
In semiconductor device fabrication, in general, excessive dislocations in a semiconductor crystal can degrade device performance due to the dislocations that provide the core for impurity deposition, resulting in micro-plasma breakdown, reversing the pn junction Wear characteristics become soft, the leakage current increases significantly, will form a pn junction in serious leakage of the channel so that the device scrapped; dislocation line impurities to enhance the proliferation, but also the formation of shallow EC channel; in general, Will also form a base subsidence effect; dislocation or noise source ....... All these are device manufacturers do not want. Therefore, the preparation of low dislocation epitaxial wafers to improve the performance of the device is very necessary.