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引言随着集成电路技术的发展,对集成度的要求越来越高,就要求有精细的技术水平,尤其要有较高的光刻套刻精度。自对准工艺对降低制版精度的要求是行之有效的方法,在金属—氧化物—半导体电路上曾有过应用。我们将自对准工艺应用于双极电路上。本试验仅涉及隔离区与基区之间的自对准,并对自对准工艺作为掩蔽用的硬Si_3N_4膜在工艺过程中出现的一些问题作了一些必要的试验。
INTRODUCTION With the development of integrated circuit technology, the requirement for integration is higher and higher, it requires a fine level of technology, in particular, have a higher lithography overlay accuracy. Self-alignment process to reduce the requirements of plate making is an effective method, has been used in metal-oxide-semiconductor circuits. We apply self-aligning technology to bipolar circuits. This test only involves the self-alignment between the isolation area and the base area, and makes some necessary tests on some problems that arise in the process of the hard Si 3 N 4 film used as a masking self-aligning process.