A low power 14 bit 51.2 kS/s double-sampling extended counting ADC with a class-AB OTA

• 作 者: 陈宏雷 伍冬 沈延钊 许军
• 机 构: Institute of Microelectronics,Tsinghua University,Beijing 100084,China,
• 出 处: 半导体学报
• 发表日期: 2012年09期
• 关键词: floating SFDR bilinear amplifier consuming operational converter eliminate analo

A 14 bit 51.2 kS/s extended counting analog to digital converter(EC-ADC) is presented.Two techniques are utilized to reduce its power consumption.First,a double-sampling configuration based on a fully-floating bilinear integrator is proposed to reduce the clock frequency.Second,a class-AB operational transconductance amplifier (OTA) is designed to improve the power efficiency.In addition,the chopping technique is used to eliminate the OTA flicker noise effect.The proposed ADC is fabricated in 0.18μm CMOS technology with a core area of 0.04 mm~2. At a 51.2 kS/s conversion rate,it achieves a 94 dB SFDR and an 11.6 bit ENOB,while consuming only 77μW from a 1.8 V power supply.The figure of merit is only 0.48 pJ/step.

A 14 bit 51.2 kS / s extended counting analog to digital converter (EC-ADC) is presented.Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilinear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier (OTA) is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of ​​0.04 mm ~ 2. At a 51.2 kS / s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 pJ / step.